The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. At the L1 level, the instruction memory holds instructions only.
#EXTERNAL MEMORY FOR MAC AIR 2012 FULL#
Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation).īlackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. The address arithmetic unit provides two addresses for simulta neous dual fetches from memory. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. Hardware is provided to support zero-over head looping.
#EXTERNAL MEMORY FOR MAC AIR 2012 PC#
For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. The program sequencer controls the flow of instruction execu tion, including instruction alignment and decoding. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. Quad 16-bit operations are possible using the second ALU.
Also provided are the compare/select and vector search instructions.įor certain instructions, two 16-bit ALU operations can be per formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). The set of video instructions includes byte alignment and packing opera tions, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. These include bit operations such as field extract and population count, modulo 2 32 multiply, divide primitives, satu ration and rounding, and sign/exponent detection. In addition, many special instructions are included to accelerate various signal processing tasks. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. Signed and unsigned formats, rounding, and saturation are supported. All operands for compute operations come from the multiported register file and instruction constant fields.Įach MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. The compute register file contains eight 32-bit registers. The compu tation units process 8-bit, 16-bit, or 32-bit data from the register file.
0 kommentar(er)
